发明授权
US5055717A Data selector circuit and method of selecting format of data output from
plural registers
失效
数据选择电路及从多个寄存器输出数据格式的方法
- 专利标题: Data selector circuit and method of selecting format of data output from plural registers
- 专利标题(中): 数据选择电路及从多个寄存器输出数据格式的方法
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申请号: US398339申请日: 1989-08-24
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公开(公告)号: US5055717A公开(公告)日: 1991-10-08
- 发明人: Atsushi Naito , Kiyoshi Nakatsuka , Seiichi Yamamoto , Takashi Inui , Tomohiro Suzuki
- 申请人: Atsushi Naito , Kiyoshi Nakatsuka , Seiichi Yamamoto , Takashi Inui , Tomohiro Suzuki
- 申请人地址: TX Dallas
- 专利权人: Texas Instruments Incorporated
- 当前专利权人: Texas Instruments Incorporated
- 当前专利权人地址: TX Dallas
- 优先权: JPX61-125454 19860530
- 主分类号: G09G5/395
- IPC分类号: G09G5/395 ; G11C7/10
摘要:
Data selector circuit including a plurality of data registers connected in parallel via corresponding output buffers to a plurality of output drivers, wherein a decoder and selector portion is interposed between the output buffers and the output drivers for selectively providing one of a plurality of serial data output sequences from the data registers to the output drivers rather than a parallel data output format from the plurality of data registers which would otherwise occur. The decoder and selector portion is controlled by a partial address buffer which is provided with serial sequence selection data. Upon decoding the serial sequence selection data of the partial address buffer, a plurality of MOS transistors included in the selector portion are rendered conductive in sequence in response to respective control signals applied to the gates thereof to connect the plurality of data registers via their output buffers to respective output drivers in a sequence determined by the decoded selection data of the partial address buffer for serial data output in the selected serial data output sequence.
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