This arrangement has an input (10) for receiving the information to be encoded in the form of fixed words comprising a number of bits, a first transcoding member (20) for applying said variable word to "n" outputs among n parallel outputs, a second transcoding member (22) for supplying from its output the indication of the length (n), and an accumulation member (30) for forming a first "modulo N" accumulated information and a second "modulo 2N" accumulated information, which are the result of operations performed on "n". A cyclic permutation circuit (32) supplies a permuted word which represents the permuted variable code word as a function of the first accumulated information, switching circuit (35) selectively transfers as a function of the second accumulated information the bits of the permuted word to a first and/or to a second register, and detection circuit (30,45) cooperates with the accumulation member for detecting the fill level of one of said registers to act on the transfer circuit so as to transfer the content of the filled register to the output.