An instruction processor for a data processing system runs arithmetic sequences that are initiated by sequence designator signals and are interrupted by interrupt signals. During operation of the processor logic elements of the processor are selectively cleared by clear signals during time periods that sequence designator signals are in inactive states following the occurrence of an interrupt signal. Dual indentical logic circuits are employed wherein each of the circuits include error circuit elements that are coupled to receive the interrupt signal and arithmetic sequence initiation signals. A comparator is coupled to an output of each of the dual identical logic circuit to receive signals that are used to indicate when an interrupt signal and an arithmetic sequence initiation signal occurs simultaneously in only one of the logic circuits. Clear sequence circuitry in each of the dual identical logic circuits receives the interrupt signal and selectively supplies clear signals to the logic elements.