发明授权
- 专利标题： Enhanced test circuit
- 专利标题（中）： 增强测试电路
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申请号： US542665申请日： 1990-06-25
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公开(公告)号： US5084874A公开(公告)日： 1992-01-28
- 发明人: Lee D. Whetsel, Jr.
- 申请人： Lee D. Whetsel, Jr.
- 申请人地址： TX Dallas
- 专利权人： Texas Instruments Incorporated
- 当前专利权人： Texas Instruments Incorporated
- 当前专利权人地址： TX Dallas
- 主分类号： G01R31/3185
- IPC分类号： G01R31/3185
摘要：
A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously.
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