A multi-processor data processing system, comprises a plurality of data processing modules. A set of interrupt lines are connected in parallel to all the processing modules. Each processing module has a priority level, and the lowest priority module is selected to act as an interrupt handler, with responsibility for handling all balanced interrupts. Whenever a processing module changes it priority, it clocks to see whether the interrupt handler is still the lowest priority module and, if not, causes the role of interrupt handler to be transferred.