发明授权
US5115510A Multistage data flow processor with instruction packet, fetch, storage
transmission and address generation controlled by destination
information
失效
具有指令分组，获取，存储传输和目的地信息控制的地址生成的多级数据流处理器
- 专利标题： Multistage data flow processor with instruction packet, fetch, storage transmission and address generation controlled by destination information
- 专利标题（中）： 具有指令分组，获取，存储传输和目的地信息控制的地址生成的多级数据流处理器
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申请号： US259722申请日： 1988-10-19
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公开(公告)号： US5115510A公开(公告)日： 1992-05-19
- 发明人: Toshiya Okamoto , Souichi Miyata
- 申请人： Toshiya Okamoto , Souichi Miyata
- 申请人地址： JPX Osaka
- 专利权人： Sharp Kabushiki Kaisha
- 当前专利权人： Sharp Kabushiki Kaisha
- 当前专利权人地址： JPX Osaka
- 优先权： JPX62-265733 19871020; JPX63-7791 19880118
- 主分类号： G06F9/44
- IPC分类号： G06F9/44
摘要：
An information processor includes a program memory for storing a data flow program having destination information and instruction information as one set. Destination information, instruction information and operand data included in an input data packet are latched in an input data latching portion. Only the operand data is transferred to an output data latching portion. An address is operated based on the destination information latched in the input data latching portion, and the program memory is accessed, so that the data flow program is read out. The destination information and the instruction information included in the read data flow program are latched in the output data latching portion. Paired data is detected by a paired data detection portion based on the data flow program latched in the output data latching portion. The detected data is operated by an operation processing portion.
公开/授权文献
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