A floating point multiplier circuit for multiplying two binary numbers includes a multiplier, a binary point processing device, a first network adder/subtracter, a second adder/subtracter, and a control device. In the floating point multiplier circuit, the circuit for operating the exponent and mantissa is designed using a parallel arrangement of PMOS and NMOS transistors. Faster operation is realized by transmitting in parallel a given input and a resulting output. Furthermore, the structure is much simpler than configurations using conventional logic gates thereby resulting in reduced chip area and efficient use of VLSI design methodologies.