Invention Grant
- Patent Title: Method of providing power to an integrated circuit
- Patent Title (中): 向集成电路提供电源的方法
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Application No.: US718524Application Date: 1991-06-21
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Publication No.: US5172471APublication Date: 1992-12-22
- Inventor: Chin C. Huang
- Applicant: Chin C. Huang
- Applicant Address: CA San Jose
- Assignee: VLSI Technology, Inc.
- Current Assignee: VLSI Technology, Inc.
- Current Assignee Address: CA San Jose
- Main IPC: H05K1/02
- IPC: H05K1/02 ; H01L23/485 ; H01L23/528 ; H01L23/64
Abstract:
A CMOS integrated circuit assembly for providing reduced power supply and ground inductances has a first conducting layer which is formed over an insulating layer formed on top of the integrated-circuit chip. The first conducting layer is connected to wire bond pads which are wirebonded to a package. This first conducting layer forms a single, low-inductance conductor for a VDD supply voltage and extends over a substantial area so that it has an inductance significantly less than the inductance of a conventional conductor. A second conducting layer is forms a low-inductance VSS conductor. Power can be selectively distributed through conductive layers of this to provide power supply isolation between selected circuits of the integrated circuit.
Public/Granted literature
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