A digital glitch filter includes first and second NOR gates coupled with feedback to form a first sampling stage, third and fourth NOR gates coupled to the output of the first and second NOR gate, respectively, and fifth and sixth NOR gates coupled with feedback to form a second sampling stage and coupled to the output of the third and fourth NOR gate, respectively, as well as three AND gates. A clock pulse generator is used to generate the pulse signals required by the glitch filter. For multiple-signal applications, the glitch filter requires relatively few gates.