A differential amplifier stage including a main pair of transistors (T1, T2) having their bases connected to a pair of input terminals (V1, V2) and their collectors coupled to a supply terminal (Vcc) via respective cascode connected transistors (T5, T6). The emitters are interconnected to a current source. An auxiliary pair of transistors (T3T4), have their bases connected to the pair of input terminals, their collectors coupled to a supply voltage (VCC'), and their emitters interconnected to a current source. A summation device supplies a part of the collector current from the auxiliary pair of transistors to the main pair of transistors. The summation device includes a first (R3, R5) and a second (R4, R6) resistor bridge coupled between the collectors of the main pair of transistors and the supply voltage (Vcc') with respective taps on the first and the second resistor bridge coupled to respective collectors for the auxiliary pair of transistors.