发明授权
- 专利标题: Semiconductor memory device with test circuit
- 专利标题(中): 具有测试电路的半导体存储器件
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申请号: US479568申请日: 1990-02-14
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公开(公告)号: US5185744A公开(公告)日: 1993-02-09
- 发明人: Kazutami Arimoto , Kazuyasu Fujishima , Yoshio Matsuda , Tsukasa Ooishi , Masaki Tsukude
- 申请人: Kazutami Arimoto , Kazuyasu Fujishima , Yoshio Matsuda , Tsukasa Ooishi , Masaki Tsukude
- 申请人地址: JPX Tokyo
- 专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX1-213560 19890818
- 主分类号: G11C29/00
- IPC分类号: G11C29/00 ; G11C11/401 ; G11C29/28 ; G11C29/34 ; G11C29/40
摘要:
A semiconductor memory device comprises a plurality of memory array blocks (B1 to B4). In each of the plurality of memory array blocks (B1 to B4), a line mode test is performed. Results of the line mode tests performed in the memory array blocks (B1 to B4) are outputted to corresponding match lines (ML1 to ML4). A flag compress (30) performs a logic operation on the test results outputted to the plurality of match lines (ML1 to ML4) and outputs the operation results as test results for the plurality of memory array blocks (B1 to B4) to the outside.