发明授权
US5187784A Integrated circuit placement method using netlist and predetermined ordering constraints to produce a human readable integrated circuit schematic diagram 失效
集成电路放置方法使用网表和预定的排序约束来生成可读的集成电路原理图

  • 专利标题: Integrated circuit placement method using netlist and predetermined ordering constraints to produce a human readable integrated circuit schematic diagram
  • 专利标题(中): 集成电路放置方法使用网表和预定的排序约束来生成可读的集成电路原理图
  • 申请号: US297353
    申请日: 1989-01-13
  • 公开(公告)号: US5187784A
    公开(公告)日: 1993-02-16
  • 发明人: James A. Rowson
  • 申请人: James A. Rowson
  • 申请人地址: CA San Jose
  • 专利权人: VLSI Technology, Inc.
  • 当前专利权人: VLSI Technology, Inc.
  • 当前专利权人地址: CA San Jose
  • 主分类号: G06F17/50
  • IPC分类号: G06F17/50
Integrated circuit placement method using netlist and predetermined
ordering constraints to produce a human readable integrated circuit
schematic diagram
摘要:
A method is disclosed for determining the placement of circuit elements in an integrated circuit where the circuit elements are initially represented by a netlist. The method preferably includes the steps of providing predetermined ordering constraints that indicate the preferred relative locations of the circuit elements that are represented in the netlist, partitioning the circuit elements from the netlist in accordance with a predetermined balancing criterion; determining the value of a cost function associated with the partitioning steps, and selecting a particular partition based upon the value of the cost function.
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