发明授权
US5189312A Multiplexer circuit having a simplified construction and reduced number
of parts
失效
多路复用器电路具有简化的结构和减少的部件数量
- 专利标题: Multiplexer circuit having a simplified construction and reduced number of parts
- 专利标题(中): 多路复用器电路具有简化的结构和减少的部件数量
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申请号: US705557申请日: 1991-05-24
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公开(公告)号: US5189312A公开(公告)日: 1993-02-23
- 发明人: Katsuya Shimizu , Tomoaki Ito
- 申请人: Katsuya Shimizu , Tomoaki Ito
- 申请人地址: JPX Kawasaki JPX Kasugai
- 专利权人: Fujitsu Limited,Fujitsu VLSI Limited
- 当前专利权人: Fujitsu Limited,Fujitsu VLSI Limited
- 当前专利权人地址: JPX Kawasaki JPX Kasugai
- 优先权: JPX2-135659 19900525
- 主分类号: H03K17/00
- IPC分类号: H03K17/00 ; H03K17/62
摘要:
A multiplexer circuit comprises a plurality of voltage generation circuits which produce corresponding output voltages having respective, different voltage levels in accordance with an ordered sequence thereof, from the lowest to the highest level. The outputs of the plurality of voltage generation circuits are supplied to a common output line. A decoder circuit receives a control data input signal which designates a selected one of the plurality of levels of the output signal and produces a signal for disabling each of the voltage generating circuits having an output voltage level of a higher order than that of the voltage generating circuit producing the output voltage of the selected level designated by the control data input signal. Voltage generating circuits of lower order need not be disabled.
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