A semiconductor memory device is fabricated from Bi-CMOS circuits and comprises a plurality of memory cells arranged in rows and columns, a plurality of word lines respectively coupled to the rows of the plurality of memory cells, a row address buffer unit coupled between first and second power voltage sources and supplied with row address bits for producing internal row address signals, a row address decoder unit responsive to the internal address signals and producing decode signals, a control signal buffer unit coupled between the first and second power voltage sources and supplied with an external control signal for producing a decode enable signal, and a word line driving unit responsive to the decode signals and selectively driving the word lines in the presence of the decode enable signal, wherein a monitoring unit is operative to monitor the power voltage level of one of the first and second power voltage sources and enables the control signal buffer unit to produce the decode enable signal when the power voltage level allows the internal address signals to become effective to the row address decoder unit so that any multiple selection of word lines never takes place.