发明授权
US5220211A High speed bus transceiver with fault tolerant design for hot pluggable
applications
失效
高速总线收发器，具有适用于热插拔应用的容错设计
- 专利标题： High speed bus transceiver with fault tolerant design for hot pluggable applications
- 专利标题（中）： 高速总线收发器，具有适用于热插拔应用的容错设计
-
申请号： US783801申请日： 1991-10-28
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公开(公告)号： US5220211A公开(公告)日： 1993-06-15
- 发明人: Robert J. Christopher , Donald J. DaCosta , Joseph C. Diepenbrock , Phillip R. Epley
- 申请人： Robert J. Christopher , Donald J. DaCosta , Joseph C. Diepenbrock , Phillip R. Epley
- 申请人地址： NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： NY Armonk
- 主分类号： H04L25/02
- IPC分类号： H04L25/02 ; G06F13/40 ; H03K19/0175 ; H04L25/08
摘要：
A high-speed data transport system for use in computers, switches, microprocessors or the like includes a low impedance differential bus and a plurality of transceivers connected to the bus. Each of the transceivers is provided with a driver circuit which places data onto the bus and a receiver for accepting data from the bus. The driver includes a pseudo-differential current driving circuit arrangement which sinks current from only one side of the bus while the other side of the differential bus is undisturbed. The receiver includes a differential comparator biased to a preferred output voltage level.
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