发明授权
US5220327A Decimation filter in a sigma-delta analog-to-digtal converter
失效
SIGMA-DELTA模拟到数字转换器中的十进制滤波器
- 专利标题: Decimation filter in a sigma-delta analog-to-digtal converter
- 专利标题(中): SIGMA-DELTA模拟到数字转换器中的十进制滤波器
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申请号: US878106申请日: 1992-05-04
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公开(公告)号: US5220327A公开(公告)日: 1993-06-15
- 发明人: Jean-Claude Abbiate , Alain Blanc , Patrick Jeanniot , Gerard Orengo , Gerard Richter
- 申请人: Jean-Claude Abbiate , Alain Blanc , Patrick Jeanniot , Gerard Orengo , Gerard Richter
- 申请人地址: NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: NY Armonk
- 优先权: EPX91480114 19910717
- 主分类号: H04B14/06
- IPC分类号: H04B14/06 ; H03H17/06
摘要:
A decimation filter for converting a train of sigma-delta pulses S(i) in synchronism with a sigma-delta clock (fs) into a train of PCM samples which includes counters (321, 331, 341) driven by the sigma-delta clock (fs) and which is continuously incremented by one during N sigma-delta clock pulses, then decremented by two during N following sigma-delta clock pulses and then incremented again by one during N following sigma-delta clock pulses in order to provide a sequence of incrementation parameter DELTA(n). The decimation filter further includes storages (320, 330, 340) for storing the value of the coefficient C(n) corresponding to the decimation filter transfer function, and incrementers (327, 337, 347) driven by the sigma-delta clock fs for incrementing the storages with the incrementation parameter DELTA(n). Finally, the decimation filter includes computers (323, 333, 343, 327, 337, 347) for deriving from the contents C(n) of said storages and from the train of input sigma-delta samples S(i+n) one Pulse Code Modulation (PCM) sample every 3.times.N input sigma-delta samples according to the formula: ##EQU1##
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