发明授权
US5229314A Method of manufacturing field effect transistor having a multilayer interconnection layer therein with tapered sidewall insulation 失效
具有其中具有锥形侧壁绝缘体的多层互连层的场效应晶体管的方法

Method of manufacturing field effect transistor having a multilayer
interconnection layer therein with tapered sidewall insulation
摘要:
A field effect transistor and a method of manufacturing thereof are disclosed that is not reduced in the characteristic of withstanding voltage between multilayer interconnection layers even when scaled to a higher integration. This field effect transistor includes side walls 21a formed on both sides of a bit line 15 so that the bottom side end contacts the upper surface of side walls 20a of gate electrodes 4b and 4c. The thickness of an insulating film interposed between gate electrodes 4b and 4c and a base portion 11a forming a low electrode 11 of a capacitor is not reduced. The characteristic of withstanding voltage is not deteriorated between multilayer interconnection layers even when scaled to higher integration.
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