发明授权
- 专利标题： Semiconductor device including complementary insulating gate field effect transistors and bipolar transistors in semiconductor substrate
- 专利标题（中）： 半导体器件包括补充绝缘栅场效应晶体管和双极晶体管在半导体衬底
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申请号： US798096申请日： 1991-11-27
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公开(公告)号： US5245209A公开(公告)日： 1993-09-14
- 发明人: Yoshiyuki Ishigaki
- 申请人： Yoshiyuki Ishigaki
- 申请人地址： JPX Tokyo
- 专利权人： Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人： Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址： JPX Tokyo
- 优先权： JPX2-400959 19901207; JPX3-298887 19911114
- 主分类号： H01L21/8249
- IPC分类号： H01L21/8249 ; H01L21/74 ; H01L27/06 ; H01L27/092
摘要：
The impurity concentration of an n.sup.+ buried layer 51a in the region for forming a p channel MOS transistor 23 is higher than the impurity concentration of an n.sup.+ buried layer 3a in the region for forming an npn bipolar transistor 21. N.sup.+ buried layers 3a and 51a are formed on a p type silicon substrate 1. An n.sup.- well region 10 is formed as a region for forming npn bipolar transistor 21 on n.sup.+ buried layer 3a. An n well region 12 is formed as a region for forming p channel MOS transistor 23 on n.sup.+ buried layer 51a. While the performance of npn bipolar transistor 21 is maintained, the performance of a CMOS transistor formed of an n channel MOS transistor 22 and p channel MOS transistor 23 is improved. In a Bi-CMOS semiconductor device, the performance of a bipolar transistor portion is maintained, while preventing the formation of a punch through and improving the latch up tolerance of a CMOS transistor portion.
公开/授权文献
- US4750196A Device for examining a body by means of gamma rays or X-rays 公开/授权日：1988-06-07
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