发明授权
- 专利标题: DCT/IDCT processor and data processing method
- 专利标题(中): DCT / IDCT处理器和数据处理方法
-
申请号: US854922申请日: 1992-03-20
-
公开(公告)号: US5249146A公开(公告)日: 1993-09-28
- 发明人: Shinichi Uramoto , Yoshitsugu Inoue
- 申请人: Shinichi Uramoto , Yoshitsugu Inoue
- 申请人地址: JPX Tokyo
- 专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX3-063259 19910327
- 主分类号: G06F7/548
- IPC分类号: G06F7/548 ; G06F1/035 ; G06F17/14 ; G06F17/16 ; G06T1/20 ; G06T9/00
摘要:
A one-dimensional discrete cosine transform processor of N (N: positive integer)-term input data X includes a preprocessing section for carrying out addition and subtraction of (i)th-term data x (i) and (N-i)th-term data x (N-1) of input data X, and a unit for performing a product sum operation for sets of intermediate data subjected to preprocessing by addition and sets of intermediate data subjected to preprocessing by subtraction, respectively. The product sum operation unit includes a data rearranging unit for outputting, in parallel and in order, bit data of the same figure of a set of data, a partial sum generator for generating a partial sum by using the parallel bit data as an address, and an accumulator for accumulating outputs of the partial sum generator. A one-dimensional inverse discrete cosine transform processor of N-term input data X includes a unit for performing a product sum operation of input data, and a postprocessing section for carrying out addition and subtraction of 2-term data in a predetermined combination of an output of the product sum operation unit. The number of times of multiplication is reduced by utilizing inherent characteristics of coefficients of DCT/IDCT processing. Since the product sum operation is performed by a ROM table and an adder, a faster multiplication is realized.
公开/授权文献
- US6122381A Stereophonic sound system 公开/授权日:2000-09-19