Auto-zeroing clocking signals, a first auto-zeroing clocking signal of comparatively-low frequency and duty cycle and a second auto-zeroing clocking signal of the same comparatively-low frequency but complementary and comparatively-high duty cycle, and a sampling clocking signal of comparatively-high frequency respectively initiate auto-zeroing of a circuit element subject to output offset error and data sampling of an A.C. input signal to a latch. The sampling of the A.C. input signal to the latch occurs at the comparatively-high frequency of the clocking signal during the "on" time of the comparatively-high duty cycle second auto-zeroing clocking signal of comparatively-low frequency enabling thereby to provide higher speed sampling than heretofore possible. The auto-zeroing of the circuit element subject to input offset error occurs during the "on" time of the comparatively-low duty cycle first auto-zeroing clocking signal of comparatively-low frequency enabling thereby to provide lower power sampling than heretofore possible. Typically, the circuit element is either an analog comparator or an operational amplifier, and the sampling circuit of the invention has exemplary utility in analog-to-digital (A/D) conversion.