发明授权
US5272673A Dynamic random access memory device with build-in test mode discriminator for interrupting electric power to row address decoder and driver for transfer gates 失效
具有内置测试模式鉴别器的动态随机存取存储器,用于中断电源到行地址解码器和驱动器的传输门

  • 专利标题: Dynamic random access memory device with build-in test mode discriminator for interrupting electric power to row address decoder and driver for transfer gates
  • 专利标题(中): 具有内置测试模式鉴别器的动态随机存取存储器,用于中断电源到行地址解码器和驱动器的传输门
  • 申请号: US824206
    申请日: 1992-01-22
  • 公开(公告)号: US5272673A
    公开(公告)日: 1993-12-21
  • 发明人: Tadahiko Sugibayashi
  • 申请人: Tadahiko Sugibayashi
  • 申请人地址: JPX Tokyo
  • 专利权人: NEC Corporation
  • 当前专利权人: NEC Corporation
  • 当前专利权人地址: JPX Tokyo
  • 优先权: JPX3-28078 19910129
  • 主分类号: G11C11/401
  • IPC分类号: G11C11/401 G11C11/407 G11C11/409 G11C29/00 G11C29/02 G11C29/04 G11C29/50
Dynamic random access memory device with build-in test mode
discriminator for interrupting electric power to row address decoder
and driver for transfer gates
摘要:
A dynamic random access memory device can enter a diagnostic mode of operation to see whether or not undesirable short-circuit takes place in a word line and/or a control signal line for transfer gates between bit lines and a sense amplifier unit, and a built-in testing operation discriminating unit discriminates the testing operation on the word lines and the control signal lines from other testing operations for causing a power supply system to interrupt electric power to a row address decoder unit and a driver unit for the control signal lines so that voltage level on a word line and/or a control signal line is rapidly decayed due to the short-circuit, thereby screening out the defective products before the delivery from the manufacturer.
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