发明授权
US5278436A Semiconductor integrated circuit device for forming logic circuit
including resistance element connected to bipolar transistor with
smaller occupied area
失效
用于形成逻辑电路的半导体集成电路器件，包括连接到具有较小占用面积的双极晶体管的电阻元件
- 专利标题： Semiconductor integrated circuit device for forming logic circuit including resistance element connected to bipolar transistor with smaller occupied area
- 专利标题（中）： 用于形成逻辑电路的半导体集成电路器件，包括连接到具有较小占用面积的双极晶体管的电阻元件
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申请号： US739144申请日： 1991-08-01
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公开(公告)号： US5278436A公开(公告)日： 1994-01-11
- 发明人: Katsushi Asahina , Masahiro Ueda
- 申请人： Katsushi Asahina , Masahiro Ueda
- 申请人地址： JPX Tokyo
- 专利权人： Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人： Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址： JPX Tokyo
- 优先权： JPX2-211367 19900808
- 主分类号： H01L21/8249
- IPC分类号： H01L21/8249 ; H01L21/82 ; H01L27/06 ; H01L27/118 ; H01L27/02 ; H01L27/10
摘要：
Disclosed is an improved Bi-CMOS gate array for increasing integration density. The gate array includes a predetermined region for forming PMOS transistors, a predetermined region for forming bipolar transistors, a predetermined region for forming resistance elements, and a predetermined region for forming NMOS transistors. The resistance element region is formed adjacent to the bipolar transistor region, and, therefore, it is not necessary to provide any interconnection for forming a logic circuit including the resistance element connected to the bipolar transistor. An area occupied by interconnections on the semiconductor substrate is thus reduced, and, therefore the integration density is increased.
公开/授权文献
- US5962113A Integrated circuit device and process for its manufacture 公开/授权日：1999-10-05
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