A digital circuit arrangement for transforming an input digital picture signal onto a reference horizontal synchronizing signal raster derived from the system clock, which input digital picture signal is present at a system clock rate not locked with the input digital picture signal, which includes a correction memory (1), an interpolator/decimator (2), and a control member for the purpose of a transformation which is as insensitive to interference as possible. The control member receives a control deviation signal (d) obtained with the aid of a discriminator (4) by comparing a horizontal synchronizing signal in the input digital picture signal with the reference horizontal synchronizing signal, and the control member applies a first correcting variable (i) to the correction memory (1), the first correcting variable (i) indicating transformation of the input digital picture signal by integral multiples of the system clock period to be performed by the correction memory (1), and the control member also applies a second correcting variable (.alpha..sub.s) to the interpolator/decimator (2), the second correcting variable (.alpha..sub.s) indicating the transformation by fractions of the system clock period to be performed by the interpolator/decimator (2).