An interrupt test circuit is provided on the same chip with a microprocessor system having a central processing unit, and an interrupt controller controlling execution of an interrupt operation of the central processing unit in response to an interrupt request signal from peripheral units. The interrupt test circuit is connected between the peripheral units and the interrupt controller and includes a test signal output connected to the interrupt controller, and storage means for storing an interrupt request test signal when receiving a predetermined signal and for supplying the test signal through the test signal output to the interrupt controller for interrupt performance test.