An address input buffer circuit for a semi-conductor storage device, comprising an input circuit 62 being controlled by an external input address signal An, an internal reference voltage signal Vref and a setup enable signal .phi.AXE; a setup circuit 63 connected to both stages of said input circuit 62; a sense amplifying circuit 61 connected to both stages of said setup circuit 63; a pair of charging circuits 67 and 68 connected to said both stages of said setup circuit 63 respectively and to a power source; a pair of hold circuits 64 and 65 connected to said both stages of said setup circuit 63 respectively; a drive circuit 66 connected to said sense amplifying circuit 61; and an output circuit 71 connected to said pair of hold circuits 64 and 65. Therefore, the address input buffer circuit for the semi-conductor storage device according to the present invention is capable of realizing a high speed operation by directly performing an address setup operation in order to remove the setup time period and therefore to shorten the access time period.