发明授权
- 专利标题: Semiconductor memory device with redundancy circuit
- 专利标题(中): 具有冗余电路的半导体存储器件
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申请号: US958466申请日: 1992-10-08
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公开(公告)号: US5289417A公开(公告)日: 1994-02-22
- 发明人: Tsukasa Ooishi , Yoshio Matsuda , Kazutami Arimoto , Masaki Tsukude , Kazuyasu Fujishima
- 申请人: Tsukasa Ooishi , Yoshio Matsuda , Kazutami Arimoto , Masaki Tsukude , Kazuyasu Fujishima
- 申请人地址: JPX Tokyo
- 专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX1-116527 19890509
- 主分类号: G11C29/00
- IPC分类号: G11C29/00
摘要:
A semiconductor memory device comprises two memory cell arrays (1a, 1b) in which a block divisional operation is performed. Two spare rows (2a, 2b) are provided corresponding to the two memory cell arrays (1a, 1b). Spare row decoders (5a, 5b) are provided for selecting the spare rows (2a, 2b), respectively. One spare row decoder selecting signal generation circuit (18) used in common by the spare row decoders (5a, 5b) is provided. The spare row decoder selecting signal generation circuit (18) can be previously set so as to generate a spare row decoder selecting signal (SRE) when a defective row exists in either of the memory cell arrays (1a, 1b) and the defective row is selected by row decoder groups (4a, 4b). Each of the spare row decoders (5a, 5b) is activated in response to the spare row decoder selecting signal (SRE) and a block control signal.
公开/授权文献
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