Techniques for providing a number of precisely synchronized clock signals at a number of different frequencies at each of a plurality of locations on a chip. A number of synchronized clock signals are generated at an initial location on the chip, and distributed to the various locations with relative delay times that are equal to within a precision, which may be less than the ultimate precision required. A single synchronization signal is also generated at the initial location, and is distributed to the remote locations with delay times that are equal to each other to a precision that corresponds to the precision required of all the clock signals. Separate synchronization circuitry at each remote location receives the clock signals and the synchronization signal, and resynchronizes the clock signals to the precision with which the synchronization signal was distributed. The set of lines is configured as a tree structure. The clock generation system has a cycle-down mode wherein all the clock frequencies are divided by a desired divisor. The frequency division occurs in response to a cycle-down signal, but the different clock frequencies are not switched until all have their rising edges aligned. The result is that the state of the machine is preserved when the clocks are cycled down.