发明授权
US5341510A Commander node method and apparatus for assuring adequate access to
system resources in a multiprocessor
失效
用于确保对多处理器中的系统资源的充分访问的指令器节点方法和装置
- 专利标题: Commander node method and apparatus for assuring adequate access to system resources in a multiprocessor
- 专利标题(中): 用于确保对多处理器中的系统资源的充分访问的指令器节点方法和装置
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申请号: US141466申请日: 1993-10-22
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公开(公告)号: US5341510A公开(公告)日: 1994-08-23
- 发明人: Richard B. Gillett, Jr. , Douglas D. Williams
- 申请人: Richard B. Gillett, Jr. , Douglas D. Williams
- 申请人地址: MA Maynard
- 专利权人: Digital Equipment Corporation
- 当前专利权人: Digital Equipment Corporation
- 当前专利权人地址: MA Maynard
- 主分类号: G06F9/46
- IPC分类号: G06F9/46 ; G06F12/00
摘要:
A multiple node computer system includes processor nodes, memory nodes, and input/output nodes interconnected on a pended bus. The system includes a lockout indicator which is set upon receipt of a locked response message by a processor node from a memory node in response to an interlock read command. The processors include a lockout check circuit responsive to the condition of the lockout indicator and will restrict generation of additional interlock read commands according to a predetermined access gating criterion until the lockout indicator is reset. In this manner, processor nodes of the system are assured equitable access to a memory node.
公开/授权文献
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