发明授权
- 专利标题: Conductivity modulation type insulated gate field effect transistor
- 专利标题(中): 电导率调制型绝缘栅场效应晶体管
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申请号: US26420申请日: 1993-03-04
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公开(公告)号: US5350934A公开(公告)日: 1994-09-27
- 发明人: Tadashi Matsuda
- 申请人: Tadashi Matsuda
- 申请人地址: JPX Kawasaki
- 专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人地址: JPX Kawasaki
- 优先权: JPX4-048316 19920305
- 主分类号: H01L29/73
- IPC分类号: H01L29/73 ; H01L21/331 ; H01L29/739 ; H01L29/78 ; H01L29/80 ; H03K17/00 ; H01L29/10
摘要:
A conductivity modulation type field effect transistor comprises an n.sup.- type low concentration impurity layer of high resistance formed on an n.sup.+ type silicon substrate, a first channel region of a given width formed on the low concentration impurity layer, a pair of p type gates oppositely formed with the first channel region therebetween, an n.sup.- type low concentration impurity layer formed on the first channel region including the p.sup.+ gate, a p channel layer including two channel regions formed on the n.sup.- type low concentration impurity layer, and a pair of n.sup.+ type sources formed on the second channel region with their center aligned with a center of the first gate means, in which, after the formation of the n.sup.+ type source, a groove is formed at each side of a respective semiconductor device, first gate electrodes are provided on the bottom surface and side wall of the groove with a gate oxide film therebetween whereby the transistor has the blocking capability of achieving a normally OFF state.
公开/授权文献
- US6044734A Pliers 公开/授权日:2000-04-04
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