A distributed VCC/VSS clamp structure (10) for preventing inadvertent damage to semiconductor integrated circuits caused by an electrostatic discharging event occurring between any two external pins thereof includes a clamp transistor (Q4) which is disposed locally to every ESD protection circuitry associated with each input and output pin of a semiconductor integrated circuit. The clamp transistor is activated so as to provide a secondary discharging path when the direct clamp discharging paths of the ESD protection circuitry are not forming a complete path.