发明授权
- 专利标题: Method for debugging in a parallel computer system and system for the same
- 专利标题(中): 并行计算机系统和系统中的调试方法
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申请号: US617782申请日: 1990-11-26
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公开(公告)号: US5361352A公开(公告)日: 1994-11-01
- 发明人: Kyoko Iwasawa , Yoshikazu Tanaka
- 申请人: Kyoko Iwasawa , Yoshikazu Tanaka
- 申请人地址: JPX Tokyo
- 专利权人: Hitachi, Ltd.
- 当前专利权人: Hitachi, Ltd.
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX1-304608 19891127
- 主分类号: G06F11/36
- IPC分类号: G06F11/36 ; G06F11/00
摘要:
In a parallel computer, a method for controlling a debugging process includes the steps of registering identifiers of plural processors into an execution waiting queue in a predetermined order; executing a corresponding program by each of the processors in an order until it is brought into either a waiting state or an end state; registering the identifier of the processor of the waiting state as a last element of the execution waiting queue; and repeating the executing step until there are no executable processors. A program having a bug is determined from the identifiers left in the execution waiting queue. Further, the debugging-process control method further includes outputting trace data during execution of the executing step, the program having the bug is determined from this trace data.
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