A preferred embodiment of this invention is a silicon-on-insulator structure comprising a semiconductor substrate (e.g. Si 36), a buried insulator layer (e.g. SiO.sub.2 34) overlaying the substrate, wherein the buried layer is buried at two or more predetermined depths, and a surface silicon layer (e.g. Si 32) overlaying the buried insulator, wherein the surface silicon layer has two or more predetermined thicknesses. Generally, by patterning and etching a screening material (e.g. SiO.sub.2 30) prior to ion implantation, preselected areas of the substrate with less or no screen material are formed with a thicker surface silicon layer, while other areas with more screen material are formed with a thinner surface silicon layer. The areas of different surface silicon thickness can be used to implement devices with different characteristics based on those thicknesses, within the same integrated circuit. Generally, relatively thinner regions can be used for faster speed devices and relatively thicker regions can be used for greater current carrying capability. The novel technique of depositing, patterning and etching a layer of screening material before implantation can also be used to create a substrate with both bulk and SOI substrate regions, with different portions of a circuit built in each region. Generally, such a substrate can be used to create integrated circuits that have high voltage isolation between different blocks of the circuit. The SOI/bulk substrate can also be used to fabricate integrated circuits which contain low voltage logic and which also regulate large amounts of current at high voltage.