发明授权
US5375211A Bus error processing system having direct bus master/CPU communication
失效
总线误差处理系统具有直接总线主/ CPU通信
- 专利标题: Bus error processing system having direct bus master/CPU communication
- 专利标题(中): 总线误差处理系统具有直接总线主/ CPU通信
-
申请号: US774640申请日: 1991-10-11
-
公开(公告)号: US5375211A公开(公告)日: 1994-12-20
- 发明人: Takashi Maruyama , Keiichi Kurakazu , Susumu Kaneko , Hiroyuki Kida
- 申请人: Takashi Maruyama , Keiichi Kurakazu , Susumu Kaneko , Hiroyuki Kida
- 申请人地址: JPX Tokyo
- 专利权人: Hitachi, Ltd.
- 当前专利权人: Hitachi, Ltd.
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX62-211186 19870825; JPX63-161884 19880629
- 主分类号: G06F11/00
- IPC分类号: G06F11/00 ; G06F11/07 ; G06F13/00 ; G06F13/32
摘要:
A bus error ascribable to a bus master module other than a central processing unit (CPU) is set as a specified factor for an exception process. When the exception process is requested, the CPU carries a corresponding service program for the exception process into execution without executing a process for altering and setting mask bits as is executed for an interrupt request. Thus, the exception process request specific to the bus error is not undesirably refused by the interrupt request etc. accepted before the bus error, and besides, a period of time which is expended before the start of the run of a service program corresponding to the bus error is shortened, with the result that the reliability of the process for the bus error attributed to the predetermined bus master module other than the CPU is enhanced.
公开/授权文献
信息查询