发明授权
US5394364A High-speed memory readout circuit using a single set of data buffers 失效
高速存储器读出电路采用单组数据缓冲器

  • 专利标题: High-speed memory readout circuit using a single set of data buffers
  • 专利标题(中): 高速存储器读出电路采用单组数据缓冲器
  • 申请号: US220979
    申请日: 1994-03-31
  • 公开(公告)号: US5394364A
    公开(公告)日: 1995-02-28
  • 发明人: Takafumi Masuda
  • 申请人: Takafumi Masuda
  • 申请人地址: JPX Tokyo
  • 专利权人: NEC Corporation
  • 当前专利权人: NEC Corporation
  • 当前专利权人地址: JPX Tokyo
  • 优先权: JPX5-075979 19930401
  • 主分类号: G11C11/41
  • IPC分类号: G11C11/41 G11C7/10 G11C11/401 G11C7/00
High-speed memory readout circuit using a single set of data buffers
摘要:
In a memory readout circuit, a data register is provided for storing data bits of a word read out of a memory cell array. Connected to the data register is a transfer gate array which is equally divided into groups of first to k-th transfer gates. First to k-th data buffers are connected respectively to the first to k-th transfer gates of different groups. One of the groups of transfer gates is selected and the transfer gates of the selected group transfers first to k-th data bits of unit data from the data register to the first to k-th data buffers, respectively. From the data bits stored in the data buffers, i-th to k-th data bits (where i is in a range from 1 to k) are selected. If i is not equal to k, the stored i-th to (k-1)th data bits are read out of the buffers to an external circuit and the k-th data bit is stored into a latch when the (k-1)th data bit is read out to the output and reads out the k-th data bit from the latch circuit to the external circuit when data bits of subsequent unit data are transferred to the data buffers. If i is equal to k, the k-th data bit is read out of the buffer to the external circuit when data bits of subsequent unit data are transferred to the data buffers.
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