发明授权
US5404489A System and method for minimizing cache interruptions by inhibiting snoop
cycles if access is to an exclusive page
失效
用于通过禁止窥探周期来最小化缓存中断的系统和方法，如果访问是专用页面
- 专利标题： System and method for minimizing cache interruptions by inhibiting snoop cycles if access is to an exclusive page
- 专利标题（中）： 用于通过禁止窥探周期来最小化缓存中断的系统和方法，如果访问是专用页面
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申请号： US236011申请日： 1994-05-02
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公开(公告)号： US5404489A公开(公告)日： 1995-04-04
- 发明人: Greg Woods , Carol Bassett , Robert Campbell
- 申请人： Greg Woods , Carol Bassett , Robert Campbell
- 申请人地址： CA Palo Alto
- 专利权人： Hewlett-Packard Company
- 当前专利权人： Hewlett-Packard Company
- 当前专利权人地址： CA Palo Alto
- 主分类号： G06F12/02
- IPC分类号： G06F12/02 ; G06F12/08 ; G06F15/16 ; G06F12/00
摘要：
A memory property tagging apparatus is interfaced with one or more caches which are associated with one or more microprocessors of a multiprocessor system having shared memory and a bus network. The apparatus masks off any snoop cycles on the bus network if data corresponding to an address is exclusive to its associated microprocessor(s). The apparatus can specify to its associated one or more caches whether data is cacheable or not. The apparatus can specify to its associated one or more caches whether data is to be treated as write-through or write-back. Finally, the apparatus can translate preselected memory addresses on the bus network into input/output (IO) addresses.
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