Invention Grant
US5406218A Phase demodulator receiving inputs from phase detector and binary phase
detector
失效
相位解调器从相位检测器和二进制相位检测器接收输入
- Patent Title: Phase demodulator receiving inputs from phase detector and binary phase detector
- Patent Title (中): 相位解调器从相位检测器和二进制相位检测器接收输入
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Application No.: US194074Application Date: 1994-02-09
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Publication No.: US5406218APublication Date: 1995-04-11
- Inventor: Yukihito Ishihara , Kazuo Yamakido , Takao Okazaki , Katsuhiro Furukawa
- Applicant: Yukihito Ishihara , Kazuo Yamakido , Takao Okazaki , Katsuhiro Furukawa
- Applicant Address: JPX Tokyo
- Assignee: Hitachi, Ltd.
- Current Assignee: Hitachi, Ltd.
- Current Assignee Address: JPX Tokyo
- Priority: JPX5-055190 19930219
- Main IPC: H03D3/20
- IPC: H03D3/20 ; H04L27/233

Abstract:
A demodulation circuit comprises: a phase detection circuit for determining an absolute value of a phase difference between an input signal to be demodulated and a reference signal; a binary phase detection circuit for converting a phase lead or lag between the input signal and the reference signal into a sign of phase difference; and a phase demodulation circuit for calculating, from the absolute value and the sign of phase difference, a phase difference quantity between the input signal and the reference signal and for performing a delay detection on the phase difference quantity; wherein the binary phase detection circuit includes a delay circuit which generates a delay time corresponding to the operation delay of the phase detection circuit; and wherein the phase detection circuit includes a level limiter circuit to limit an internal signal voltage and a reference voltage adjust circuit to correct deviations in the internal signal voltage.
Public/Granted literature
- USD303373S Battery Public/Granted day:1989-09-12
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