An interface circuit which is connected between a peripheral device and a computer and which can conduct a data transfer at a higher speed. When a first digital data D.sub.1 is output from a peripheral device, the transfer of a memory bus enable request signal DRQ to a computer is halted by transfer control means, and the first digital data is output from the peripheral device in accordance with a false read control signal FIOR from an interface circuit, and held in hold means. When a second digital data is output from the peripheral device, DRQ is transferred to the computer, and 2N-bit data, i.e., N-bit second digital data D.sub.2 output from the peripheral device, and the N-bit first digital data D.sub.1 which is held are simultaneously transferred to the computer in accordance with a read control signal IOR from the computer.