发明授权
US5410171A Vertical type semiconductor with main current section and emulation
current section
失效
具有主电流部分和仿真电流部分的垂直型半导体
- 专利标题： Vertical type semiconductor with main current section and emulation current section
- 专利标题（中）： 具有主电流部分和仿真电流部分的垂直型半导体
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申请号： US038951申请日： 1993-03-29
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公开(公告)号： US5410171A公开(公告)日： 1995-04-25
- 发明人: Yasuaki Tsuzuki , Akira Kuroyanagi , Toshiaki Nishizawa
- 申请人： Yasuaki Tsuzuki , Akira Kuroyanagi , Toshiaki Nishizawa
- 申请人地址： JPX Kariya
- 专利权人： Nippondenso Co., Ltd.
- 当前专利权人： Nippondenso Co., Ltd.
- 当前专利权人地址： JPX Kariya
- 优先权： JPX4-074534 19920330
- 主分类号： H01L21/336
- IPC分类号： H01L21/336 ; H01L21/76 ; H01L27/02 ; H01L27/04 ; H01L29/06 ; H01L29/10 ; H01L29/78
摘要：
A power DMOS semiconductor device providing improved current detection accuracy can be produced using standard pocessess. The device includes main wells, subwells and a line well which is independent of the main wells and subwells. These wells are formed by doping the surface of a semiconductor substrate with well-forming impurities. The line well surrounds the subwells at a predetermined distance away from the subwells to relax an electric field on the surface of the substrate. Gate electrodes are patterned to form a line opening which surrounds the subwells. The line opening serves as a mask when forming the line well by doping the surface of the substrate with the well-forming impurities. Accordingly, the width of a region between the line well and an adjacent subwell will not fluctuate.
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