发明授权
US5418923A Circuit for prioritizing outputs of an associative memory with parallel
inhibition paths and a compact architecture
失效
用于对具有并行抑制路径和紧凑架构的关联存储器的输出进行优先级排列的电路
- 专利标题: Circuit for prioritizing outputs of an associative memory with parallel inhibition paths and a compact architecture
- 专利标题(中): 用于对具有并行抑制路径和紧凑架构的关联存储器的输出进行优先级排列的电路
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申请号: US937763申请日: 1992-09-01
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公开(公告)号: US5418923A公开(公告)日: 1995-05-23
- 发明人: Masaaki Mihara , Tadato Yamagata , Takeshi Hamamoto
- 申请人: Masaaki Mihara , Tadato Yamagata , Takeshi Hamamoto
- 申请人地址: JPX Tokyo
- 专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX3-221691 19910902; JPX4-140801 19920601
- 主分类号: G11C15/04
- IPC分类号: G11C15/04 ; G11C15/00
摘要:
An encoding circuit shortens time required for a coincidence signal to be converted into an address code after selected and output sequentially according to a predetermined priority level when the coincidence signal is obtained from an associative memory. The circuit is provided with a contention arbitrating circuit for a lower subgroup and a contention arbitrating circuit for a higher subgroup. In the contention arbitrating circuit for a lower subgroup and the contention arbitrating circuit for higher subgroup, each coincidence signal simultaneously activates inhibiting signals whose priority levels are lower than the priority level of the coincidence signal. A lower half of coincidence signals are arranged in descending order in the contention arbitrating circuit for a lower subgroup and a higher half of coincidence signals are arranged in ascending order in the contention arbitrating circuit for a higher subgroup. The contention arbitrating circuit for a lower subgroup and the contention arbitrating circuit for a higher subgroup are arranged in a triangular array and a complementary triangular array, respectively.
公开/授权文献
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