发明授权
- 专利标题： Transistor arrangement for forming basic cell of master-slice type semiconductor integrated circuit device and master-slice type semiconductor integrated circuit device
- 专利标题（中）： 用于形成主片式半导体集成电路器件和母片型半导体集成电路器件的基本单元的晶体管布置
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申请号： US365173申请日： 1994-12-28
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公开(公告)号： US5436485A公开(公告)日： 1995-07-25
- 发明人: Junichi Shikatani , Tetsu Tanizawa , Mitsugu Naito
- 申请人： Junichi Shikatani , Tetsu Tanizawa , Mitsugu Naito
- 申请人地址： JPX Kanagawa
- 专利权人： Fujitsu Limited
- 当前专利权人： Fujitsu Limited
- 当前专利权人地址： JPX Kanagawa
- 优先权： JPX3-178121 19910718
- 主分类号： H01L27/118
- IPC分类号： H01L27/118 ; H01L27/02 ; H01L27/10
摘要：
A master-slice type semiconductor integrated circuit device includes a first transistor, and a second transistor. The first and second transistors are arranged side by side in a first direction. The first and second transistors respectively have first and second gate electrodes extending in a second direction perpendicular to the first direction. The first gate electrode has a first portion in which two gate contacts arranged in the first direction can be made. The second gate electrode has a second portion in which two gate contacts arranged in the first direction can be made.
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