发明授权
- 专利标题: AFC circuit for QPSK demodulator
- 专利标题(中): 用于QPSK解调器的AFC电路
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申请号: US306957申请日: 1994-09-16
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公开(公告)号: US5440268A公开(公告)日: 1995-08-08
- 发明人: Noboru Taga , Tatsuya Ishikawa , Susumu Komatsu
- 申请人: Noboru Taga , Tatsuya Ishikawa , Susumu Komatsu
- 申请人地址: JPX Kawasaki
- 专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人地址: JPX Kawasaki
- 优先权: JPX5-229780 19930916
- 主分类号: H04L27/22
- IPC分类号: H04L27/22 ; H04L27/00 ; H04L27/233 ; H03D3/00
摘要:
AFC circuit for QPSK demodulator including, a circuit for obtaining quadrature related detection signals by multiplying a modulated input signal with quadrature related local oscillation frequency signals from a quadrature phase local oscillator, digital converter for converting the detection signals into corresponding digital signals by sampling them with quadrature related clocks which have a frequency two times higher than a symbol rate of the input signal, frequency error detecter for detecting a frequency error between the quadrature related digital signals using a symbol timing sample value and a symbol intermediate timing sample value in the converted digital signals, first validity determinator for determining whether the frequency error signal is valid or not through a detection of the pattern of the modulated input signal from sample values before and after the symbol timing so as to result a first validity signal, second validity determinator for deetermining whether the frequency error signal is valid or not through a detection of an absolute sample value of the symbol intermediate timing so as to result a second validity signal, and valid frequency error extractor for extracting the frequency error signal as a frequency control signal for controlling the oscillation frequency of the local oscillator when the frequency error signal has been proved to be valid by the first and the second validity signals.
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