发明授权
- 专利标题: Logic circuit synthesizer
- 专利标题(中): 逻辑电路合成器
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申请号: US53007申请日: 1993-04-27
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公开(公告)号: US5452230A公开(公告)日: 1995-09-19
- 发明人: Hiroyuki Mori , Yoshio Inoue
- 申请人: Hiroyuki Mori , Yoshio Inoue
- 申请人地址: JPX Tokyo
- 专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人: Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX4-114702 19920507
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
A logic circuit synthesizer is disclosed which synthesizes a better dimensioned logic circuit which has improved electrical characteristics. A logic circuit leveling part levels logic circuit data while referring to a leveling dictionary and maintaining logic function frames to thereby output leveled logic circuit data which contains information about logic function frames. The leveled logic circuit data are then given to a logic circuit synthesizing part where they are leveled using a conversion library and considering the information about logic function frames, whereby synthesized logic circuit data are produced. Since the synthesizing is performed in light of the information about logic function frames and what are prescribed in the conversion library a resultant synthesized logic circuit is improved in terms of both electrical characteristics and a dimension accuracy.
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