发明授权
US5453391A Method for manufacturing a contactless floating gate transistor array
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非接触式浮栅晶体管阵列的制造方法
- 专利标题: Method for manufacturing a contactless floating gate transistor array
- 专利标题(中): 非接触式浮栅晶体管阵列的制造方法
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申请号: US67519申请日: 1993-05-25
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公开(公告)号: US5453391A公开(公告)日: 1995-09-26
- 发明人: Tom D. Yiu , Fuchia Shone , Tien-Ler Lin , Ling Chen
- 申请人: Tom D. Yiu , Fuchia Shone , Tien-Ler Lin , Ling Chen
- 申请人地址: TWX Hsinchu
- 专利权人: Macronix International Co., Ltd.
- 当前专利权人: Macronix International Co., Ltd.
- 当前专利权人地址: TWX Hsinchu
- 主分类号: G11C16/04
- IPC分类号: G11C16/04 ; H01L21/8247 ; H01L27/115
摘要:
An improved contactless EPROM array, EPROM cell design, and method for fabricating the same is based on a unique drain-source-drain configuration, in which a single source diffusion is shared by two columns of transistors. An elongated first drain diffusion region, an elongated source diffusion region, and an elongated second drain diffusion region, are formed in a semi-conductor substrate along essentially parallel lines. Field oxide regions are grown on opposite sides of the first and second drain diffusion regions. Floating gates and control gate wordlines are formed orthogonal to the drain-source-drain structure to establish two columns of storage cells having a shared source region. The shared source region is coupled through a bottom block select transistor to a virtual ground terminal. Each drain diffusion region is coupled through a top block select transistor to global bitline. The cell structure uses two metal global bitlines which extend essentially parallel to the drain, source and drain diffusion regions, and a virtual ground conductor which couples a plurality of columns of transistors to a virtual ground terminal through a horizontal conductor, such as a buried diffusion line.
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