发明授权
US5455438A Semiconductor integrated circuit device in which kink current
disturbances of MOS transistors are suppressed
失效
其中抑制了MOS晶体管的扭矩电流干扰的半导体集成电路器件
- 专利标题: Semiconductor integrated circuit device in which kink current disturbances of MOS transistors are suppressed
- 专利标题(中): 其中抑制了MOS晶体管的扭矩电流干扰的半导体集成电路器件
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申请号: US69572申请日: 1993-06-01
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公开(公告)号: US5455438A公开(公告)日: 1995-10-03
- 发明人: Naotaka Hashimoto , Toshiaki Yamanaka , Takashi Hashimoto , Akihiro Shimizu , Nagatoshi Ohki , Hiroshi Ishida
- 申请人: Naotaka Hashimoto , Toshiaki Yamanaka , Takashi Hashimoto , Akihiro Shimizu , Nagatoshi Ohki , Hiroshi Ishida
- 申请人地址: JPX Tokyo JPX Tokyo
- 专利权人: Hitachi, Ltd.,Hitachi VLSI Engineering Corp.
- 当前专利权人: Hitachi, Ltd.,Hitachi VLSI Engineering Corp.
- 当前专利权人地址: JPX Tokyo JPX Tokyo
- 优先权: JPX3-253472 19911001
- 主分类号: H01L21/762
- IPC分类号: H01L21/762 ; H01L27/105 ; H01L27/088
摘要:
Disclosed is a semiconductor integrated circuit device having a plurality of fine memory devices and its fabrication method, and particularly to a semiconductor integrated circuit device capable of suppressing the kink current disturbance of MOS transistors without reducing the junction characteristic of the diffusion layers and its fabrication method. In this device, an angle between the lower surface of each edge of a field oxide formed in an environmental device area, i.e. a peripheral circuit area, and the main surface of a semiconductor substrate is smaller than an angle between the lower surface of each edge of a field oxide formed in a memory cell area and the main surface of the semiconductor substrate. Further, the extension, in the direction of being parallel to the main surface of the semiconductor substrate, of each edge of the field oxide in the environmental device area is larger than the extension, in the direction of being parallel to the main surface of the semiconductor substrate, of each edge of the field oxide in the memory cell area.
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