A method of testing a digital integrated circuit for faults. A plurality of n check points l.sub.1, l.sub.2, . . . , l.sub.n are established to define a test sequence. A set of m references r.sub.1, r.sub.2, . . . , r.sub.m are predefined, corresponding to the signatures which the circuit would produce at the corresponding check points in the absence of any faults. A test sequence is applied to the circuit and an output signature s.sub.i is derived from the circuit at the corresponding check point l.sub.i. The output signature is compared with each member of the set of references. The circuit is declared "good" if the signature matches at least one member of the set of references, or "bad" if a signature matches no members of the set of references. Testing proceeds in similar fashion at the next check point, until the circuit has been tested at all check points.