发明授权
US5487017A Circuit activity driven multilevel logic optimization for low power
reliable operation
失效
电路活动驱动的多电平逻辑优化用于低功率可靠运行
- 专利标题: Circuit activity driven multilevel logic optimization for low power reliable operation
- 专利标题(中): 电路活动驱动的多电平逻辑优化用于低功率可靠运行
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申请号: US18984申请日: 1993-02-18
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公开(公告)号: US5487017A公开(公告)日: 1996-01-23
- 发明人: Sharat Prasad , Kaushik Roy
- 申请人: Sharat Prasad , Kaushik Roy
- 申请人地址: TX Dallas
- 专利权人: Texas Instruments Incorporated
- 当前专利权人: Texas Instruments Incorporated
- 当前专利权人地址: TX Dallas
- 主分类号: G06F17/50
- IPC分类号: G06F17/50 ; H03M5/20 ; H03M5/00
摘要:
A method and apparatus for optimizing a boolean network. The boolean network contains a plurality of functions and a plurality of nodes. Any cube-free divisors (a divisor in which no cube divides the divisor evenly) in the boolean network which apply to at least two of the functions are located (108). The greatest divisor, which is defined as the cube-free divisor which brings about the largest net savings, is determined (114). The net savings comprises both an area savings component and a power savings component. Once the greatest divisor is determined, it is replaced with a variable in each of the functions (116) and added to the boolean network as a new function to create an optimized boolean network (118).
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