- 专利标题: Data processor in which external sync signal may be selectively inhibited
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申请号: US434292申请日: 1995-05-03
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公开(公告)号: US5493686A公开(公告)日: 1996-02-20
- 发明人: Haruo Keida , Takashi Tsukamoto , Nobutaka Nagasaki
- 申请人: Haruo Keida , Takashi Tsukamoto , Nobutaka Nagasaki
- 申请人地址: JPX Tokyo JPX Tokyo
- 专利权人: Hitachi, Ltd.,Hitachi Microcomputer Engineering Ltd.
- 当前专利权人: Hitachi, Ltd.,Hitachi Microcomputer Engineering Ltd.
- 当前专利权人地址: JPX Tokyo JPX Tokyo
- 优先权: JPX60-184207 19850823
- 主分类号: G06F1/10
- IPC分类号: G06F1/10 ; G06F1/04 ; G06F15/78
摘要:
An external sync signal generated by a clock generation circuit inside a single-chip microcomputer is supplied to an external terminal of this chip. The external sync signal is necessary in an external expansion mode but not in a single-chip mode. Therefore, the external sync signal is supplied to the external terminal through a control gate while a suitable control signal is inputted to a control terminal of the control gate. According to this circuit construction, control can be made in such a manner that the external sync signal is not supplied to the output terminal in the single-chip mode. As a result, it becomes possible to prevent noise from entering a signal supplied to an adjacent pin through a coupling capacity between the external terminals in the single-chip mode, and to reduce consumed power of an output buffer circuit which is disposed between the control gate and the external terminals.
公开/授权文献
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