发明授权
- 专利标题： Fabrication process for multilevel interconnections in a semiconductor device
- 专利标题（中）： 半导体器件中多电平互连的制造工艺
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申请号： US394943申请日： 1995-02-24
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公开(公告)号： US5506177A公开(公告)日： 1996-04-09
- 发明人: Koji Kishimoto , Tetsuya Homma
- 申请人： Koji Kishimoto , Tetsuya Homma
- 申请人地址： JPX Tokyo
- 专利权人： NEC Corporation
- 当前专利权人： NEC Corporation
- 当前专利权人地址： JPX Tokyo
- 优先权： JPX6-030667 19940228
- 主分类号： H01L23/522
- IPC分类号： H01L23/522 ; H01L21/768 ; H01L21/44
摘要：
After forming lower level wiring and plasma oxide layer, SOG film is applied by applying a solution containing hydrogen silsesquioxane as primary component under rotation. Pre-baking of the SOG film is performed by a first heat treatment and causes reflow thereof by a second heat treatment at a temperature higher than the first heat treatment. Subsequently, another plasma oxide layer is formed. By this, in an interlayer insulation layer including SOG film, occurrence of crack and so forth can be prevented and water resistance can be improved.
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