A device for switching packets at high speed. For each packet, the A device matches packet data with protocols, to determine how to switch the packet. Matching of data with protocols is highly parallel; the device simultaneously retrieves a data byte, compares a data byte with a protocol byte, tests a comparison result, and executes a processor instruction. A switching engine having a comparator and a decision tree memory. The comparator includes three outputs for indicating a comparison result (less-than, equal-to, or greater-than). The tree memory includes three corresponding banks of addressable memory. Each memory location comprises an entry for a next location, an entry for a next protocol byte, and an entry for a processor instruction. A set of protocol tests are assembled into the tree memory, and a set of routing tables are dynamically generated into the tree memory.