发明授权
US5509132A Semiconductor memory device having an SRAM as a cache memory integrated
on the same chip and operating method thereof
失效
具有集成在同一芯片上的作为高速缓存存储器的SRAM的半导体存储器件及其操作方法
- 专利标题： Semiconductor memory device having an SRAM as a cache memory integrated on the same chip and operating method thereof
- 专利标题（中）： 具有集成在同一芯片上的作为高速缓存存储器的SRAM的半导体存储器件及其操作方法
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申请号： US283487申请日： 1994-08-01
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公开(公告)号： US5509132A公开(公告)日： 1996-04-16
- 发明人: Yoshio Matsuda , Kazuyasu Fujishima , Hideto Hidaka , Mikio Asakura
- 申请人： Yoshio Matsuda , Kazuyasu Fujishima , Hideto Hidaka , Mikio Asakura
- 申请人地址： JPX Tokyo
- 专利权人： Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人： Mitsubishi Denki Kabushiki Kaisha
- 当前专利权人地址： JPX Tokyo
- 优先权： JPX2-098782 19900413
- 主分类号： G06F12/08
- IPC分类号： G06F12/08 ; G11C7/10 ; G11C8/00 ; G11C11/401 ; G11C11/41
摘要：
A cache DRAM (100) includes a DRAM memory array (11) accessed by a row address signal and a column address signal, an SRAM memory array (21) accessed by the column address signal, and an ECC circuit (30). The DRAM memory array (11) is divided into a plurality of blocks (B1 to B64), each including a plurality of columns. The SRAM memory array (21) includes 4 ways (W1 to W4). In determining a cache hit/cache miss, a column address signal is inputted. Consequently, the SRAM memory array (21) is accessed and data are read from each of the ways. When a cache hit occurs, one way is selected in response to an externally applied way address signal, and data from that way are outputted. When a cache miss occurs, the column address signal is latched and the row address signal is applied. The DRAM array (11) is accessed in accordance with the row address signal and the latched column address signal.
公开/授权文献
- US5051859A Current-limiting load cutout 公开/授权日：1991-09-24
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